The present disclosure relates generally to electronic memory circuits, and more particularly to complementary metal oxide semiconductor (CMOS) static random access memories (SRAM). Still more particularly, the present disclosure relates to methods of placing these memories in, and of recovering these circuits from, a standby mode.
Electronic memory circuits have been known for many years. Such memory circuits have employed a wide variety of types of circuits and circuit elements in order to store information in some way, such as by storage of charge in a capacitive element or the use of a bistable circuit or element. Such a bistable element can take the form, for example, of the well-known flip-flop circuit, where a pair of transistors are cross-coupled in such a way that when one transistor is turned on, the other will be forced off, or a magnetizable core or other element or domain which can be selectively magnetized into one of at least two distinct states.
Each of these memory types, categorized by the type of memory cell employed, has distinct advantages and disadvantages with respect to the other types of memory and each type will typically be applied where the advantages can be best utilized.
With widespread use of electronic devices for operating portable appliances such as portable telephones, personal digital assistants (PDA), portable information terminals, AV devices and others on batteries, it is becoming more important to decrease both power consumption during operation and power consumption during device standby mode.
In recent years, there has been an interest in increasing the memory capacity of all types of memory devices, including static memory devices. Some particular problems are encountered in doing so in SRAMs because the size of each memory cell on the chip is much larger than in dynamic RAMs due to the use of a greater number of circuit elements in each memory cell. SRAMs have the advantage over dynamic RAMs by demonstrating significantly higher switching speeds and have the ability to be put in a standby mode, which significantly reduces total memory current.
SRAMs are comprised of gate-insulated field-effect transistors, or MOS transistors. These transistors require an operating voltage that decreases as the transistor size decreases, because the breakdown voltage of the transistor decreases with the smaller size. As well, the threshold voltage (VT) of the MOS transistor must be lowered in accordance with the drop of operating voltage so as to retain high-speed operation, because the operating speed is dominated by the effective gate voltage of the MOS transistor (i.e., the operating voltage minus VT), and increases as the difference increases.
Generally speaking, however, if the VT is lower than about 0.4 V, a direct sub-threshold current, which exponentially increases with the drop in VT, will flow through the MOS transistor, which should intrinsically be cut off. As a result, the direct current greatly increases in a semiconductor integrated circuit composed of a number of MOS transistors, even if the circuit is a CMOS circuit. This sub-threshold current is significant when multiplied by the large number of memory cells in current memory arrays and produces undesirable standby power consumption during standby.
The most popular and simplest method of reducing power involves reducing the applied operating voltage to the entire memory during the standby mode. This approach requires a longer charge time to retrieve the first information from the memory upon recovery from the standby mode. It also requires a high current charging current during the switching from the standby to operating condition. For large bit density SRAMs, lower power consumption is important for device thermal stability, power bus design and product specification. Thus a standby circuit model is widely used in SRAM circuit design.
Desirable in the art of semiconductor memory design are method and circuit designs for operating devices under their standby mode.